Product Summary

The XC95108-15PC84C is a CPLD. The XC95108-15PC84C provides advanced in-system programming and test capabilities for high performance, general purpose logic integration. All devices are in-system programmable for a minimum of 10,000 program/erase cycles. Extensive IEEE 1149.1 (JTAG) boundary-scan support is also included on all family members.

Parametrics

XC95108-15PC84C absolute maximum ratings: (1)VCC Supply voltage relative to GND: -0.5 to 7.0 V; (2)VIN DC input voltage relative to GND: -0.5 to VCC + 0.5 V; (3)VTS Voltage applied to 3-state output with respect to GND: -0.5 to VCC + 0.5 V; (4)TSTG Storage temperature: -65 to +150℃; (5)TSOL Max soldering temperature (10 s @ 1/16 in = 1.5 mm): +260℃.

Features

XC95108-15PC84C features: (1)High-performance: 5 ns pin-to-pin logic delays on all pins; fCNT to 125 MHz; (2)Large density range: 36 to 288 macrocells with 800 to 6,400 usable gates; (3)5V in-system programmable: Endurance of 10,000 program/erase cycles; Program/erase over full commercial voltage and ; (4)temperature range; (5)Enhanced pin-locking architecture; (6)Flexible 36V18 Function Block: 90 product terms drive any or all of 18 macrocells within Function Block; (7)Global and product term clocks, output enables, set and reset signals; (8)Extensive IEEE Std 1149.1 boundary-scan (JTAG) support; (9)Programmable power reduction mode in each macrocell; (10)Slew rate control on individual outputs; (11)User programmable ground pin capability; (12)Extended pattern security features for design protection; (13)Advanced CMOS 5V FastFLASH technology; (14)Supports parallel programming of multiple XC9500 devices.

Diagrams

XC95108-15PC84C Architecture

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XC95108-15PC84C
XC95108-15PC84C


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IC REG BUCK ADJ 1A DL 10MSOP

Data Sheet

0-1: $1.19
1-10: $1.07
10-25: $0.96
25-100: $0.86
100-250: $0.77
250-500: $0.67