EPM9480RC208-15

Product Summary

The EPM9480RC208-15 in-system-programmable, high-density, highperformance EPLD is based on Altera third-generation MAX architecture. Fabricated on an advanced CMOS technology, the EEPROM based EPM9480RC208-15 provides 6,000 to 12,000 usable gates, pin-to-pin delays as fast as 10 ns, and counter speeds of up to 144 MHz. The -10 speed grade of the EPM9480RC208-15 is compliant with the PCI Local Bus Specification, Revision 2.2.

Parametrics

EPM9480RC208-15 absolute maximum ratings: (1)VCC Supply voltage: =2.0 to 7.0 V; (2)VI DC input voltage: =2.0 to 7.0 V; (3)VCCISP Supply voltage during in-system programming: =2.0 to 7.0 V; (4)IOUT DC output current, per pin: =25 to 25 mA; (5)TSTG Storage temperature No bias: =65 to 150 ℃; (6)TAMB Ambient temperature Under bias: =65 to 135 ℃; (7)TJ Junction temperature Ceramic packages, under bias: 150 ℃; (8)PQFP and RQFP packages, under bias: 135 ℃.

Features

EPM9480RC208-15 features: (1)High-performance CMOS EEPROM-based programmable logic devices (PLDs) built on third-generation Multiple Array MatriX (MAXR) architecture; (2)5.0-V in-system programmability (ISP) through built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface; (3)Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990; (4)High-density erasable programmable logic device (EPLD) family ranging from 6,000 to 12,000 usable gates; (5)10-ns pin-to-pin logic delays with counter frequencies of up to 144 MHz; (6)Fully compliant with the peripheral component interconnect Special Interest Group乫s (PCI SIG) PCI Local Bus Specification, Revision 2.2; (7)Dual-output macrocell for independent use of combinatorial and registered logic; (8)Input/output registers with clear and clock enable on all I/O pins; (9)Programmable output slew-rate control to reduce switching noise; (10)MultiVolt. I/O interface operation, allowing devices to interface with 3.3-V and 5.0-V devices; (11)Configurable expander product-term distribution allowing up to 32 product terms per macrocell; (12)Programmable power-saving mode for more than 50% power reduction in each macrocell.

Diagrams